Profile picture for user svmula
Dr. Subrahmanyam Mula
Assistant Professor
Email Me

Subrahmanyam Mula received the B.E. degree in electronics and communication engineering from Andhra University, Visakhapatnam in 2001, and the M.Tech. degree in microelectronics and VLSI design from IIT Kharagpur in 2003, and Ph.D. degree from Department of Electronics and Electrical Communication Engineering, IIT Kharagpur in 2018. From 2003 to 2014, he was with Intel, Bengaluru where he was involved in front-end design verification of gigabit Ethernet switches, processors, chip-sets, and GPUs. He supported six generations of Intel GPUs from Eaglelake (Gen4) on 65nm to Skylake (Gen9) on 14nm at various levels such as architecture, RTL, Verification, GLS, STA, DFT and Post Si Debug. His current research interests include VLSI architectures for real time signal processing applications and adaptive learning systems.


My research interests span the broad area of VLSI architectures for statistical signal processing algorithms. My current research mainly focuses on developing efficient VLSI architectures for real-time adaptive filtering applications. For achieving the best performance-flexibility trade-off of the complex adaptive filtering algorithms, I focus on co-design of algorithm and architecture in an intertwined way rather than designing them in isolation. 


· Digital Systems (UG) (July - Dec 2019, July - Dec 2020, Aug - Dec 2021) 

· Digital Circuits Lab (UG) (July - Dec 2019, Aug - Dec 2022)

· VLSI Architectures for signal processing and machine learning (Theory & Lab) (UG & PG)  (Jan - May 2020, Feb - May 2021, Jan - May 2022)

. VLSI Design (Theory & Lab) (PG) (July - Dec 2020, Aug - Dec 2021, Aug - Dec 2022)

Research Group

PhD Students: 


     1. Ganjimala Pavankumar (PMRF Fellow, July 2020 - ) , Research Area : Algorithms and architectures for nonlinear adaptive filtering applications

     2. Rooha Ramzid Ahamed (July 2022 - ), Research area : VLSI architectures for real-time signal processing/machine learning applications

     3. Jayarani M A (July 2022 - ) (Jointly with Dr. Sabarimalai Manikandan) , Research area :  Low power VLSI architectures for biomedical signal processing


MS Students: 


     1. Vishnu P S (July 2022 - ) , Research area: VLSI signal processing


    1. Daney Alex (Jan 2020 - September 2022) , Thesis title: VLSI Architectures for Adaptive Filters under non-Gaussian Signal and Noise Conditions



Research Area
VLSI Signal Processing
Digital VLSI Circuits and Systems
Adaptive Signal Processing
Additional Information
Sponsored Projects
Project Title Funding Agency Duration Role
HARKAL: Hardware Accelerated Robust Kernel Adaptive Learning Start-up Research Grant (SERB) Jan 2021 - Jan 2023 PI
Energy Efficient Distributed Estimation and Control of Networked Robots and its Implementation Architectures IIT Palakkad Technology IHub Foundation (IPTIF) June 2021 - June 2026 Co-PI






1. D. Alex, V. C. Gogineni, S. Mula and S. Werner, "Novel VLSI Architecture for Fractional-order Correntropy Adaptive Filtering Algorithm", in IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 30, no. 7, pp. 893-904, July 2022.

2. S. R. K. Vadali, S. Mula, P. Ray and S. Chakrabarti, "Area Efficient VLSI Architectures for Weak Signal Detection in Additive Generalized Cauchy Noise," in IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 67, no. 6, pp. 1962-1975, June 2020.

3. S. Mula, V. C. Gogineni, A. S. Dhar, “Robust Proportionate Adaptive Filter Architectures under Impulsive Noise,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 27, no.5, pp. 1223-1227, May 2019.

4. S. Mula, V. C. Gogineni, A. S. Dhar, “Algorithm and VLSI Architecture Design of Proportionate-type LMS Adaptive Filters for Sparse System Identification,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 26, no.9, pp. 1750-1762, Sept. 2018.

5. V. C. Gogineni and S. Mula, “Proportionate-type Adaptive Filtering under Maximum Correntropy Criterion for Identifying Systems with Variable Sparsity,” Digital Signal Processing (ELSEVIER), vol. 79, pp. 190-198, Aug. 2018.  

6. V. C. Gogineni and S. Mula, “Logarithmic Cost based Constrained Adaptive Filtering Algorithms for Sensor Array Beamforming,”  IEEE Sensors Journal, vol. 18, no. 14, pp. 5897-5905, July 2018.

7. S. Mula, V. C. Gogineni, A. S. Dhar, “Algorithm and Architecture Design of Adaptive Filters With Error Nonlinearities,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 25, no. 9, pp. 2588-2601, Sept. 2017.  

8. B. K. N. Srinivasarao, V. C. Gogineni, S. Mula, and I. Chakrabarti, “A Novel Framework for Compressed Sensing based Scalable Video Coding”, Signal Processing: Image Communication (ELSEVIER), vol. 57, pp. 183-196, Sept. 2017.

9. S. R. K. Vadali, P. Ray, S. Mula, and P. K. Varshney, “Linear Detection of a Weak Signal in Additive Cauchy Noise,” IEEE Transactions on Communications, vol. 65, no. 3, pp. 1061-1076, March 2017.  


1.  P. Ganjimala and S. Mula, "High performance VLSI architecture for the modified SORT-N algorithm",  IEEE International Symposium on Circuits and Systems (ISCAS), Austin, Texas, 2022 (Accepted)

2. V. C. Gogineni, S. Mula, R. L. Das and M. Chakraborty, “Performance analysis of proportionate-type LMS algorithms,“ 2016 Signal Processing: Algorithms, Architectures, Arrangements, and Applications (SPA), Poznan, Poland, 2016, pp. 177-181.

Invited Talks

"CAD for Digital VLSI Design" as part of the five day online workshop on "The Art of IC design using EDA tools" held from 15th-19th March, 2021 at Cochin University of Science and Technology, Kochi 

Recent Publications

Daney Alex; Vinay Chakravarthi Gogineni; Subrahmanyam Mula; Stefan Werner
IEEE Transactions on Very Large Scale Integration (VLSI) Systems (2022)
Siva Ram Krishna Vadali; Subrahmanyam Mula; Priyadip Ray; Saswat Chakrabarti
IEEE Transactions on Circuits and Systems I: Regular Papers 67 (6) 1962 - 1975 (2020)
Subrahmanyam Mula ; Vinay Chakravarthi Gogineni ; Anindya Sundar Dhar
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 27 (5) 1223 - 1227 (2019)