Subrahmanyam Mula received the B.E. degree in electronics and communication engineering from Andhra University, Visakhapatnam, India, in 2001, and the M.Tech. degree in microelectronics and VLSI design from IIT Kharagpur, Kharagpur, India, in 2003, and Ph.D. degree from Department of Electronics and Electrical Communication Engineering, IIT Kharagpur, Kharagpur, India, in 2018. From 2003 to 2014, he was with Intel, Bengaluru, India, where he was involved in front-end design verification of gigabit Ethernet switches, processors, chip-sets, and GPUs. He has experience in building strong design verification teams, leading them, coordinating with multiple stake holders across sites (India, US, Israel and Malaysia) and delivering to projects. He supported six generations of Intel GPUs from Eaglelake (Gen4) on 65nm to Skylake (Gen9) on 14nm at various levels such as architecture, RTL, Verification, GLS, STA, DFT and Post Si Debug. He made significant contributions to 32nm Sandy Bridge processor that first time integrated 4 high performance Intel Architecture (IA) cores, a power/performance optimized GPU, memory and PCIe controllers in the same die. His current research interests include VLSI architectures for real time signal processing applications and adaptive learning systems.
.
My research interests span the broad area of VLSI architectures for statistical signal processing algorithms. My current research mainly focuses on developing efficient VLSI architectures for real-time adaptive filtering applications. For achieving the best performance-flexibility trade-off of the complex adaptive filtering algorithms, I focus on co-design of algorithm and architecture in an intertwined way rather than designing them in isolation.
July - Dec 2019:
· Digital Systems
· Digital Circuits Lab
Jan - May 2020:
· VLSI Architectures for signal processing and machine learning (Theory & Lab)
Journals:
1. S. R. K. Vadali, S. Mula, P. Ray and S. Chakrabarti, "Area Efficient VLSI Architectures for Weak Signal Detection in Additive Generalized Cauchy Noise," in IEEE Transactions on Circuits and Systems I: Regular Papers, 2020 (in early access)
2. S. Mula, V. C. Gogineni, A. S. Dhar, “Robust Proportionate Adaptive Filter Architectures under Impulsive Noise,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 27, no.5, pp. 1223-1227, May 2019.
3. S. Mula, V. C. Gogineni, A. S. Dhar, “Algorithm and VLSI Architecture Design of Proportionate-type LMS Adaptive Filters for Sparse System Identification,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 26, no.9, pp. 1750-1762, Sept. 2018.
4. S. Mula, V. C. Gogineni, A. S. Dhar, “Algorithm and Architecture Design of Adaptive Filters With Error Nonlinearities,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 25, no. 9, pp. 2588-2601, Sept. 2017.
5. V. C. Gogineni and S. Mula, “Logarithmic Cost based Constrained Adaptive Filtering Algorithms for Sensor Array Beamforming,” IEEE Sensors Journal, vol. 18, no. 14, pp. 5897-5905, July 2018.
6. V. C. Gogineni and S. Mula, “Proportionate-type Adaptive Filtering under Maximum Correntropy Criterion for Identifying Systems with Variable Sparsity,” Digital Signal Processing (ELSEVIER), vol. 79, pp. 190-198, Aug. 2018.
7. S. R. K. Vadali, P. Ray, S. Mula, and P. K. Varshney, “Linear Detection of a Weak Signal in Additive Cauchy Noise,” IEEE Transactions on Communications, vol. 65, no. 3, pp. 1061-1076, March 2017.
8. B. K. N. Srinivasarao, V. C. Gogineni, S. Mula, and I. Chakrabarti, “A Novel Framework for Compressed Sensing based Scalable Video Coding”, Signal Processing: Image Communication (ELSEVIER), vol. 57, pp. 183-196, Sept. 2017.
Conferences:
V. C. Gogineni, S.Mula, R. L. Das andM. Chakraborty, “Performance analysis of proportionate-type LMS algorithms,“ 2016 Signal Processing: Algorithms, Architectures,Arrangements, and Applications (SPA), Poznan, Poland, 2016, pp. 177-181.
04923 226 300 (Office)
netadmin@iitpkd.ac.in