Energy Efficient Multicore Programmable Accelerator for ULP massive edge computing
Laboratoires: Indian Institute of Technology (IIT) Palakkad/ Lab for Advanced VLSI and System Architecture (LAVA), Kerala, India
Université de Bretagne Sud/Lab-STICC (UMR 6285, CNRS), Lorient, France
With the increased market space of new computing paradigm such as Internet of Things (IoT), Cyber-Physical Systems (CPS) etc., the typical High-Performance Computing (HPC) applications initially deployed with no energy constraints are now foreseen in embedded devices with stringent energy budget. For example, application domains like artificial intelligence and cryptography criticized for their high energy consumption, are now needed in battery supplied devices. The solution for optimal energy efficient devices is completely design specific, which is very costly, time consuming, with returns on investment for very large volumes of sales only.
Due to the increasing demand for ultra-low power computing, and diminishing returns from technology scaling, industry and academia are turning with renewed interest toward energy efficient hardware accelerators in multi-core heterogeneous systems. The main drawback of hardware accelerators is that they are not programmable. Therefore, their utilization can be low as they perform one specific function and increasing the number of the accelerators in a system on chip (SoC) causes scalability issues. Programmable accelerators provide flexibility and solve the scalability issues.