vivek

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Dr. Vivek Chaturvedi
Asst. Professor
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Biosketch

Assistant Professor, IIT Palakkad  (July 2018 - Present)

 

Research Scientist, Nanyang Technological University, Singapore, (September 2013 - July 2018),

 

Summer Intern, Sun Microsystems, Burlington, MA, USA (May 2007 - August 2007)

 

 

Education

  • Ph.D. Electrical Engineering,                                                                                                     

Florida International University, Miami, FL, USA                                                                                 

  • M.S. Electrical Engineering,                                                                                                   

Syracuse University, Syracuse, NY, USA                                                                                                 

  • B.E. Electronics & Communication Engineering,                                                                 

            Rajiv Gandhi Technical University, Bhopal, MP, India                                       

 

Research Interests

  • Power and thermal efficient task scheduling strategies for multi/many core processors
  • Reliability and energy efficiency in cloud data centers
  • Cyber (hardware) security
  • Artificial Intelligence

 

Research Proposal Grants & Academic Awards

  • NTU Edex Grant, Co-PI title: Concept Visualization and simulation web portal to support study of abstract topics in computer architecture: (SGD$39,000)
  • Assisted in writing research proposal title: Variation-tolerant dynamic thermal management for protecting multi-core processors under temperature constraint based on adaptive fuzzy control : Hong Kong GRF (HK$ 329361)
  • Syracuse University Dean’s scholarship for academic excellence (Spring 2008)
  • Syracuse University Dean’s scholarship for academic excellence (Fall & Spring 2007)

 

 

Publications

Peer-Reviewed Journals

  • B. Zhou, W. Zhang, T. Srikanthan, V. Chaturvedi, “Cost-efficient Acceleration of Hardware Trojan Detection through Fan-out Cone Analysis and Weighted Random Pattern Technique”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 35, No. 5, pg. 792-805, April 2016
  • Y. Cui, V. Chaturvedi, W. Zhang, H. He, “Decentralized Thermal-aware Scheduling with Deadline Constraints for Large-scale Network-on-Chip”, IEEE Transactions on Very Large Scale Integration Systems, Vol. PP, pg. 1-14, November 2015
  • Y. Cui, V. Chaturvedi, W. Zhang, H. He, “Thermal-Aware Task Scheduling for 3D-Network-on-Chip:A Bottom to Top Scheme”, Journal of Circuits, Systems, and Computers Vol. 25, No. 1 (2016), October 2015
  • H. Huang, V. Chaturvedi, G. Quan, “Throughput Maximization for Periodic Real-Time Systems under the Maximal Temperature Constraint”, ACM Transactions on Embedded Computing Systems (TECS), Vol. 13, No. 2, pg. 1-19, 2014
  • V. Chaturvedi, H. Huang, S. Ren, G. Quan, “On the Fundamentals of Leakage Aware Real-Time DVS Scheduling for Peak Temperature Minimization”, Journal of Systems Architecture (JSA), Vol. 58, No. 10, pg. 387-397, 2012
  • H. Huang, V. Chaturvedi, G. Quan, “Leakage Aware Scheduling On Maximum Temperature Minimization For Periodic Hard Real-Time SystemsJournal of Low Power Electronics, Vol. 8, No. 4, pg. 378-393, 2012
  • G. Quan, V. Chaturvedi,Feasibility Analysis for Temperature-Constraint Hard Real-time Periodic TasksIEEE Transactions on Industrial Informatics (TII), Vol. 6, No. 3, pg. 329-339, 2010

 

Selected Conferences

  • V. Rathore, V. Chaturvedi, A.K. Singh, T. Srikanthan and M. Shafique , " HiMap: Aging-aware Hierarchical Mapping Approach for Darksilicon Manycore Systems", IEEE/ACM/SIGDA 21st  Design, Automation & Test in Europe Conference & Exhibition (DATE ), 2018 (accepted)
  • Rohith R, V. Rathore, V. Chaturvedi, A.K. Singh, T. Srikanthan and S.K. Lam ,” LifeSim: A Lifetime Reliability Simulator for Manycore Systems”, IEEE 8th Annual Computing and Communication Workshop and Conference (CCWC), 2018 (accepted)
  • Z. Zhu, V. Chaturvedi, A.K. Singh, W. Zhang and Y. Cui, "Two-stage Thermal-Aware Scheduling of Task Graphs on 3D Multi-cores Exploiting Application and Architecture Characteristics", IEEE 22nd Asia and South Pacific Design Automation Conference (ASP-DAC) 2017, pg.324-329
  • V. Rathore, V. Chaturvedi, T. Srikanthan,"Performance Constraint-Aware Task Mapping to Optimize Lifetime Reliability of Manycore Systems", ACM 16th Great Lakes Symposium on VLSI (GLSVLSI) 2016, pg. 377-380
  • V. Chaturvedi, B.K. Mohanty, T. Srikanthan, “Leakage-Aware Intra-Task Dynamic Voltage Scaling Technique for Energy Reduction in Real-Time Embedded Systems”, IEEE International Conference on Digital Signal Processing (DSP) 2015,  pg. 1266-1269
  • B.K. Mohanty, V. Chaturvedi, V. Rathore, T. Srikanthan, “Memory-Access Aware Work-Load Distribution for Peak-Temperature Reduction of 3D Multi-core Embedded Systems”, IEEE International Conference on Digital Signal Processing (DSP) 2015, pg. 1270-1273
  • V. Chaturvedi, A. Singh, W. Zhang, T. Srikanthan, “Thermal-Aware Task Scheduling for Peak Temperature Minimization under Periodic Constraint for 3D-MPSoCs”, IEEE Symposium on Rapid System Prototyping (RSP) 2014, pg. 107-113
  • Y. Cui, V. Chaturvedi, W. Zhang, H. He, “Thermal-aware Task Scheduling for 3D Network-on-Chip: A Bottom to Top Scheme”, IEEE International Symposium on Integrated Circuits (ISIC) 2014, pg.  224-227
  • M. Fan, V. Chaturvedi, S. Sha, G. Quan, “An Analytical Solution For Multi-Core Energy Calculation With Consideration Of Leakage And Temperature Dependency”, IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED 2013, 353-358
  • M. Fan, V. Chaturvedi, S. Sha, G. Quan, “Feasibility Analysis for Temperature Constrained Real-Time Scheduling on Multi-Core Platforms”, IEEE/ACM Design Automation Conference (wip-DAC), 2013
  • M. Fan, V. Chaturvedi, S. Sha, G. Quan, “Thermal-Aware Energy Minimization for Real-Time Scheduling on Multi-core Systems”, IEEE Real-Time Systems Symposium (WiP-RTSS), 2012
  • V. Chaturvedi, G. Quan, “Leakage Conscious DVS Scheduling for Peak Temperature Minimization”, IEEE/ACM Asia and South Pacific Design Automation Conference (ASP-DAC), Yokohama, Japan, 2011 pg. 135-140 (Acceptance ratio: 30.7%)
  • V. Chaturvedi, P. Thanarungroj, C. Liu, G. Quan, “Validation of Scheduling Techniques to Reduce Peak Temperature on an Architectural Level Platform Set-up”, IEEE SoutheastCon, 2011, pg. 111-116
  • V. Chaturvedi, H. Huang, G. Quan, “Leakage Aware Scheduling On Maximal Temperature Minimization For Periodic Hard Real-Time Systems”, The 7th IEEE International Conference on Embedded Software and Systems (ICESS), Bradford, UK, June 29-July 01, 2010, pg. 1802-1809 (Acceptance ratio 28%)

 

Presentation and Talks

  • ACM/IEEE DATE 2018, HiMap: Aging-aware Hierarchical Mapping Approach for Darksilicon Manycore Systems”, Dresden, Germany, March 2018
  • University of Guelph, Secure and Reliable Manycore Computing Systems” Guelph, Canada, January 2018
  • IEEE DSP 2015,Leakage-Aware Intra-Task Dynamic Voltage Scaling Technique for Energy Reduction in Real-Time Embedded Systems” Singapore
  • IEEE DSP 2015,Memory-Access Aware Work-Load Distribution for Peak-Temperature Reduction of 3D Multi-core Embedded Systems” Singapore
  • Real-Time Systems Symposium (WiP)-2012,Thermal-Aware Energy Minimization for Real-Time Scheduling on Multi-core Systems”, San Juan, PR, USA
  • ASP-DAC 2011, “Leakage Conscious DVS Scheduling for Peak Temperature Minimization”, Yokohama, Japan
  • SoutheastCon 2011, “Validation of Scheduling Techniques to Reduce Peak Temperature on an Architectural Level Platform Set-up”, Nashville, TN, USA

 

Technical Review Services

  • TPC for International Symposium on VLSI (ISVLSI, 2018)
  • TPC for ICT: Big Data, Cloud and Security Conference (ICT-BDCS) 2017
  • IEEE Transaction on VLSI
  • IEEE Transactions on Parallel and Distributed Computing
  • IEEE Transactions on Multimedia
  • IEEE Transaction on Technology Computer Aided Design
  • IEEE Transaction on Computers
  • IEEE International Symposium on Circuits and Systems
  • IEEE/ACM Asia and South Pacific Design Automation Conference
  • IEEE  International Conference on Embedded and Real-Time Computing Systems and Applications
  • International Conference on Embedded Software and Systems
  • Frontier of Computer Science and Technology
  • European Symposium on Algorithms

 

Students

  • Vijeta Rathore (PhD Candidate, NTU Singapore)
  • Zuomin Zhu (PhD Student, HKUST, Hong Kong)
  • Rohan Sood (Scantist, Singapore)
  • Mohan Chouhan (Intel, USA)

 

 

Collaborators:

  • Prof. Gang Quan, Florida International University, Miami
  • Prof. Thambipillai Srikanthan, Nanyang Technological University, Singapore
  • Prof. Wei Zhang, Hong Kong University of Science and Technology, Hong Kong
  • Prof. Muhammad Shafique, Vienna University of Technology (TU-Wien), Vienna
  • Prof. Amit Kumar Singh, University of Essex
  • Prof. Sharad Sinha, Indian Institute of Technology, Goa
  • Prof. Lam Siew Kei, Nanyang Technological University, Singapore
  • Dr. Alok Prakash, Nanyang Technological University, Singapore
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