Satyajit Das is an Assistant Professor in the Department of Computer Science and Engineering, IIT Palakkad. He received his joint Ph.D. degree from University of South Brittany (UBS), France, and University of Bologna (UniBo), Italy. Prior to joining IIT Palakkad, he was a postdoctoral fellow at LabSTICC, UBS.
His research spans the areas of architecture, methods, and tools for embedded systems, including CGRAs, custom processors, multi-cores, high-level synthesis, and compilers. The main focus of Dr. Das's research is to implement highly energy efficient solutions for digital architectures in the domain of heterogeneous and reconfigurable multi-core System on Chips (SoCs). This includes architectures, design implementation strategies, runtime, and compilation support.
CS5509 - Embedded Systems
CS5613 - Cryptography
CS2610 - Computer Organization Lab
CS5104 - Big Data Analytics
CS5102 - System on Chip Design
Dec 2020 - Funding received from the Science and Engineering Research Board (SERB), Government of India under the scheme of Startup Research Grant (SRG)
Title - Energy-Efficient Multicore Programmable Accelerator for ULP massive edge computing
Funding Amount - INR 16,24,980 for 2 years
Role - Principal Investigator (PI)
Chilankamol Sunny, 2020 - present
Anju Rose G Punneliparambil, 2020 - present
Shine Parekkadan Sunny, 2020 - present
CREDS Inaugural Symposium - Kerala, India, Feb 22, 2020: Speaker, Organiser
ICASSP 2020 - Barcelona, May 4 - 8, 2020: Session Chair
SiPS 2020 - Virtual conference, 20-22 October 2020: Special Session Chair
PAKDD 2021 - Workshop on Smart and Precise Agriculture: Organizing Committee
[1] Rohit Prasad, Satyajit Das, Kevin Martin, Giuseppe Tagliavini, Philippe Coussy, Luca Benini and Davide Rossi, "TRANSPIRE: An energy-efficient TRANSprecision floating-point Programmable archItectuRE", In Proceedings of Design, Automation & Test in Europe Conference & Exhibition (DATE). IEEE, 2020, ACCEPTED
[2] S. Das, D. Rossi, K. Martin, D. Rossi, P. Coussy, L. Benini,"An Energy-Efficient Integrated Programmable Array Accelerator and Compilation flow for Near-Sensor Ultra-low Power Processing," in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD). doi: 10.1109/TCAD.2018.2834397
[3] S. Das, J. Bhaumik, “A Fault Based Attack on MDS-AES,” International Journal of Network Security (IJNS) 2014, Vol. 16, No. 2, pp. 184-189
[4] S. Das, K. Martin, P. Coussy, “Context-memory Aware Mapping for Energy Efficient Acceleration with CGRAs", In Proceedings of Design, Automation & Test in Europe Conference & Exhibition (DATE). IEEE, 2019
[5] S. Das, K. Martin, D. Rossi, P. Coussy, L. Benini, “Efficient Mapping of CDFG onto Coarse Grained Reconfigurable Array Architectures”, In Proceedings of 22nd Asia and South Pacific Design Automation Conference (ASP-DAC), Tokyo, Japan, 2017, pp. 127-132
[6] S. Das, T. Peyret, K. Martin, G. Corre, M. Thevenin, P. Coussy,” A Scalable Design Approach to Efficiently Map Applications on CGRAs,” In Proceedings of IEEE Computer Society Annual Symposium on VLSI (ISVLSI), Pittsburgh, PA, 2016, pp. 655-660
[7] S. Das, D. Rossi, K. Martin, P. Coussy, L. Benini, “A 142MOPS/mW Integrated Programmable Array accelerator for Smart Visual Processing”, In Proceedings of IEEE International Symposium on Circuits and Systems (ISCAS), Baltimore, MD, 2017, pp. 1-4
[8] S. Das, K. Martin, P. Coussy, D. Rossi, “A Heterogeneous Cluster with Reconfigurable Accelerator for Energy Efficient Near-Sensor Data Analytics”, In Proceedings of IEEE International Symposium on Circuits and Systems (ISCAS), Florence, IT, 2018 pp. 1-5
[9] V. Saraswat, D. Feldman and D. F. Kune, S. Das, “Remote Cache-timing Attacks Against AES”, In Proceedings of the First Workshop on Cryptography and Security in Computing Systems (CS2 ’14). ACM, Vienna, Austria, pp. 45-48
[10] S. Das, J. Bhaumik, “Strengthening SPN type block cipher architecture against Fault attack”, In Proceedings of IEE Int. Conf. on Communications, Devices and Intelligent Systems (CODIS) 2012, 580-583
[11] S. Das, T. Peyret, K. Martin, P. Coussy, “Introduction d’aléas dans le processus deprojection d’applications sur CGRA,” Conférence d’informatique en Parallélisme, Architecture et Système (COMPAS 2016), Jul 2016, Lorient, France
[12] S. Das, J. Bhaumik, “Compact Implementation of AES on FPGA”, In Proceedings of National Conf. of Advanced Communication and Designing (NCACD), 2011, pp. 32-34
04923 226 300 (Office)
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