satyajitdas

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Dr. Satyajit Das
Assistant Professor
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Biosketch

Satyajit Das is an Assistant Professor in the Department of Computer Science and Engineering, IIT Palakkad. He received his joint Ph.D. degree from University of South Brittany (UBS), France, and University of Bologna (UniBo), Italy. Prior to joining IIT Palakkad, he was a postdoctoral fellow at LabSTICC, UBS.

Research

His research spans the areas of architecture, methods, and tools for embedded systems, including CGRAs, custom processors, multi-cores, high-level synthesis, and compilers. The main focus of Dr. Das's research is to implement highly energy efficient solutions for digital architectures in the domain of heterogeneous and reconfigurable multi-core System on Chips (SoCs). This includes architectures, design implementation strategies, runtime, and compilation support.

Teaching

CS5009 - Embedded Systems

Research Area
Embedded Systems, Coarse Grained Reconfigurable Array, Multi-core System on Chip
Low Power Design
Reconfigurable Computing
Digital Architecture
Cryptography
High Level Synthesis
Additional Information
Title
Publications
Description

[1] Rohit Prasad, Satyajit Das, Kevin Martin, Giuseppe Tagliavini, Philippe Coussy, Luca Benini and Davide Rossi, "TRANSPIRE: An energy-efficient TRANSprecision floating-point Programmable archItectuRE", In Proceedings of Design, Automation & Test in Europe Conference & Exhibition (DATE). IEEE, 2020, ACCEPTED

[2] S. Das, D. Rossi, K. Martin, D. Rossi, P. Coussy, L. Benini,"An Energy-Efficient Integrated Programmable Array Accelerator and Compilation flow for Near-Sensor Ultra-low Power Processing," in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD). doi: 10.1109/TCAD.2018.2834397

[3] S. Das, J. Bhaumik, “A Fault Based Attack on MDS-AES,” International Journal of Network Security (IJNS) 2014, Vol. 16, No. 2, pp. 184-189

[4] S. Das, K. Martin, P. Coussy, “Context-memory Aware Mapping for Energy Efficient Acceleration with CGRAs", In Proceedings of Design, Automation & Test in Europe Conference & Exhibition (DATE). IEEE, 2019 

[5] S. Das, K. Martin, D. Rossi, P. Coussy, L. Benini, “Efficient Mapping of CDFG onto Coarse Grained Reconfigurable Array Architectures”, In Proceedings of 22nd Asia and South Pacific Design Automation Conference (ASP-DAC), Tokyo, Japan, 2017, pp. 127-132


[6] S. Das, T. Peyret, K. Martin, G. Corre, M. Thevenin, P. Coussy,” A Scalable Design Approach to Efficiently Map Applications on CGRAs,” In Proceedings of IEEE Computer Society Annual Symposium on VLSI (ISVLSI), Pittsburgh, PA, 2016, pp. 655-660


[7] S. Das, D. Rossi, K. Martin, P. Coussy, L. Benini, “A 142MOPS/mW Integrated Programmable Array accelerator for Smart Visual Processing”, In Proceedings of IEEE International Symposium on Circuits and Systems (ISCAS), Baltimore, MD, 2017, pp. 1-4


[8] S. Das, K. Martin, P. Coussy, D. Rossi, “A Heterogeneous Cluster with Reconfigurable Accelerator for Energy Efficient Near-Sensor Data Analytics”, In Proceedings of IEEE International Symposium on Circuits and Systems (ISCAS), Florence, IT, 2018 pp. 1-5


[9] V. Saraswat, D. Feldman and D. F. Kune, S. Das, “Remote Cache-timing Attacks Against AES”, In Proceedings of the First Workshop on Cryptography and Security in Computing Systems (CS2 ’14). ACM, Vienna, Austria, pp. 45-48

[10] S. Das, J. Bhaumik, “Strengthening SPN type block cipher architecture against Fault attack”, In Proceedings of IEE Int. Conf. on Communications, Devices and Intelligent Systems (CODIS) 2012, 580-583


[11] S. Das, T. Peyret, K. Martin, P. Coussy, “Introduction d’aléas dans le processus deprojection d’applications sur CGRA,” Conférence d’informatique en Parallélisme, Architecture et Système (COMPAS 2016), Jul 2016, Lorient, France

[12] S. Das, J. Bhaumik, “Compact Implementation of AES on FPGA”, In Proceedings of National Conf. of Advanced Communication and Designing (NCACD), 2011, pp. 32-34
 

Title
Open Research Positions
Description

Research positions are open for graduate, senior-level undergraduate, and postgraduate students interested in doing research on architecture and compilation support for ultra-low power accelerators, co-processors for post-quantum cryptography and machine learning applications in modern multi-core heterogeneous systems. The following skill sets are desired:

  • Programming with one or more of the following: C/C++/scripting languages
  • Knowledge about architecture, processor, memory
  • Knowledge of Hardware Description Language (HDL) (i.e. Verilog)
  • Knowledge of compilation flow, high-level synthesis

Do not hesitate to contact me, e.g., by email for further details.

Title
Miscellaneous
Description

I recommend watching You and Your Research by Richard Hamming.

Recent Publications

Rohit Prasad, Satyajit Das, Kevin Martin, Giuseppe Tagliavini, Philippe Coussy, Luca Benini and Davide Rossi
Proceedings of Design, Automation & Test in Europe Conference & Exhibition (DATE). IEEE, 2020 ACCEPTED (2020)
Satyajit Das, Kevin JM Martin, Davide Rossi, Philippe Coussy, Luca Benini
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 38 (6) 1095 - 1108 (2019)
Satyajit Das, Kevin Martin, Philippe Coussy
In Poceedings of Design, Automation and Test in Europe Conference (DATE), 2019 1 (1) 336-341 (2019)