Satyajit Das is an Assistant Professor in the Department of Computer Science and Engineering, IIT Palakkad. He received his joint Ph.D. degree from University of South Brittany (UBS), France, and University of Bologna (UniBo), Italy. Prior to joining IIT Palakkad, he was a postdoctoral fellow at LabSTICC, UBS.
His research spans the areas of architecture, methods, and tools for embedded systems, including CGRAs, custom processors, multi-cores, high-level synthesis, and compilers. The main focus of Dr. Das's research is to implement highly energy efficient solutions for digital architectures in the domain of heterogeneous and reconfigurable multi-core System on Chips (SoCs). This includes architectures, design implementation strategies, runtime, and compilation support.
CS5509 - Embedded Systems
CS5613 - Cryptography
CS2610 - Computer Organization Lab
CS5104 - Big Data Analytics
CS5102 - System on Chip Design
CS5620 - Computer Vision
NPTEL (noc22-cs83) - Applied Accelerated Artificial Intelligence
Dec 2020 - Funding received from the Science and Engineering Research Board (SERB), Government of India under the scheme of Startup Research Grant (SRG)
Title - Energy-Efficient Multicore Programmable Accelerator for ULP massive edge computing
Funding Amount - INR 16,24,980 for 2 years
Role - Principal Investigator (PI)
Dec 2020 - IPTIF
Title - Cyber-Physical Systems in Collaboration with Artificial Intelligence for Smart Agriculture
Funding for 5 years
Role - Principal Investigator (PI)
Dec 2020 - Naval Research Board
Title - Ocean Acoustic Data Archival and Analytics Framework
Funding for 2 years
Role - Co-Principal Investigator (CoPI)
Research Cluster for Artificial Intelligence - Multicoreware Academia Global Innovation Centre (MAGIC) - Multicoreware
Role - Principal Investigator
Chilankamol Sunny, 2020 - present [IIT Palakkad] - "Energy Efficient Loop Acceleration on CGRAs"
Christie Sajitha, 2022 - present [IIT Palakkad, University of South Brittany, France] - "Energy Efficient Multi-core Programmable Accelerator for ULP massive edge computing"
Shine Parekkadan Sunny, 2020 - present [IIT Palakkad] - "Low Power and High-Throughput Accelerator Architectures for DNNs"
Bijin Elsa Baby, 2021 - present [IIT Palakkad] - "Ultra Low Power Software Hardware Approach for Edge Vision"
Parvathy Ramakrishnan P - "Novel DataFrame Design for Big Data Applications"
Anju Rose P - "Low Power Architecture Model support for CGRAs Coupled with In-Memory Processing"
Alenkruth Murali, Crypto extension of RISCV ISA
Now Ph.D. student at University of Virginia
CREDS Inaugural Symposium - Kerala, India, Feb 22, 2020: Speaker, Organiser
SiPS 2020 - Virtual conference, 20-22 October 2020: Special Session Chair
PAKDD 2021 - Workshop on Smart and Precise Agriculture: Organizing Committee
SiPS 2021 - Program Committee Member
HiPC 2021 - Program Committee Member
AI Siksha on "Accelerated AI" 2022 - Instructor
Das, S., Martin, K., Rossi, D., Coussy, P., & Benini, L. (2018). An energy-efficient integrated programmable array accelerator and compilation flow for near-sensor ultralow power processing. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 38(6), 1095–1108.
Das, S., Rossi, D., Martin, K., Coussy, P., & Benini, L. (2017). A 142MOPS/mW integrated programmable array accelerator for smart visual processing. In 2017 IEEE International Symposium on Circuits and Systems (ISCAS) (pp. 1–4).
Das, S., Peyret, T., Martin, K., Corre, G., Thevenin, M., & Coussy, P. (2016). A scalable design approach to efficiently map applications on cgras. In 2016 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) (pp. 655–660).
Das, S., Martin, K., Coussy, P., Rossi, D., & Benini, L. (2017). Efficient mapping of CDFG onto coarse-grained reconfigurable array architectures. In 2017 22nd Asia and South Pacific Design Automation Conference (ASP-DAC) (pp. 127–132).
Prasad, R., Das, S., Martin, K., Tagliavini, G., Coussy, P., Benini, L., & Rossi, D. (2020). TRANSPIRE: An energy-efficient TRANSprecision floating-point Programmable archItectuRE. In 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE) (pp. 1067–1072).
Das, S. (2018). Architecture and Programming Model Support for Reconfigurable Accelerators in Multi-Core Embedded Systems. (Doctoral dissertation, Lorient).
Das, S., Martin, K., Peyret, T., & Coussy, P. (2016). Introduction d'aléas dans le processus de projection d'applications sur CGRA. In Conférence d’informatique en Parallélisme, Architecture et Syst\`eme (COMPAS 2016).
Das, S., Martin, K., & Coussy, P. (2019). Context-memory aware mapping for energy efficient acceleration with cgras. In 2019 Design, Automation & Test in Europe Conference & Exhibition (DATE) (pp. 336–341).
Das, S., Martin, K., Coussy, P., & Rossi, D. (2018). A heterogeneous cluster with reconfigurable accelerator for energy efficient near-sensor data analytics. In 2018 IEEE International Symposium on Circuits and Systems (ISCAS) (pp. 1–5).
Das, A., Das, S., & Bhaumik, J. (2013). Design of RS (255, 251) Encoder and Decoder in FPGA. international journal of soft computing and engineering, 2(6), 2231–2307.
Das, S., & Bhaumik, J. (2014). A Fault Based Attack on MDS-AES.. IJ Network Security, 16(3), 179–184.
Saraswat, V., Feldman, D., Kune, D., & Das, S. (2014). Remote cache-timing attacks against AES. In Proceedings of the First Workshop on Cryptography and Security in Computing Systems (pp. 45–48).
Das, S., Martin, K., & Coussy, P. (2019). Prise en compte de la contrainte de mémoire de programme dans un flot de compilation pour CGRA. Journal is required!.
Das, S., Prasad, R., Martin, K., & Coussy, P. (2020). Energy Efficient Acceleration of Floating Point Applications onto CGRA. In ICASSP 2020-2020 IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP) (pp. 1563–1567).
Jain, H., Rathore, S., Rahoof, T., Chaturvedi, V., & Das, S. (2020). Fast and Efficient Decision-Based Attack for Deep Neural Network on Edge. In 2020 IEEE Workshop on Signal Processing Systems (SiPS) (pp. 1–6).
Prasad, R., Das, S., Martin, K., & Coussy, P. (2021). Floating Point CGRA based Ultra-Low Power DSP Accelerator. Journal of Signal Processing Systems, 1–13.