satyajitdas

[1] Rohit Prasad, Satyajit Das, Kevin Martin, Giuseppe Tagliavini, Philippe Coussy, Luca Benini and Davide Rossi, "TRANSPIRE: An energy-efficient TRANSprecision floating-point Programmable archItectuRE", In Proceedings of Design, Automation & Test in Europe Conference & Exhibition (DATE). IEEE, 2020, ACCEPTED

[2] S. Das, D. Rossi, K. Martin, D. Rossi, P. Coussy, L. Benini,"An Energy-Efficient Integrated Programmable Array Accelerator and Compilation flow for Near-Sensor Ultra-low Power Processing," in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD). doi: 10.1109/TCAD.2018.2834397

[3] S. Das, J. Bhaumik, “A Fault Based Attack on MDS-AES,” International Journal of Network Security (IJNS) 2014, Vol. 16, No. 2, pp. 184-189

[4] S. Das, K. Martin, P. Coussy, “Context-memory Aware Mapping for Energy Efficient Acceleration with CGRAs", In Proceedings of Design, Automation & Test in Europe Conference & Exhibition (DATE). IEEE, 2019 

[5] S. Das, K. Martin, D. Rossi, P. Coussy, L. Benini, “Efficient Mapping of CDFG onto Coarse Grained Reconfigurable Array Architectures”, In Proceedings of 22nd Asia and South Pacific Design Automation Conference (ASP-DAC), Tokyo, Japan, 2017, pp. 127-132

[6] S. Das, T. Peyret, K. Martin, G. Corre, M. Thevenin, P. Coussy,” A Scalable Design Approach to Efficiently Map Applications on CGRAs,” In Proceedings of IEEE Computer Society Annual Symposium on VLSI (ISVLSI), Pittsburgh, PA, 2016, pp. 655-660

[7] S. Das, D. Rossi, K. Martin, P. Coussy, L. Benini, “A 142MOPS/mW Integrated Programmable Array accelerator for Smart Visual Processing”, In Proceedings of IEEE International Symposium on Circuits and Systems (ISCAS), Baltimore, MD, 2017, pp. 1-4

[8] S. Das, K. Martin, P. Coussy, D. Rossi, “A Heterogeneous Cluster with Reconfigurable Accelerator for Energy Efficient Near-Sensor Data Analytics”, In Proceedings of IEEE International Symposium on Circuits and Systems (ISCAS), Florence, IT, 2018 pp. 1-5

[9] V. Saraswat, D. Feldman and D. F. Kune, S. Das, “Remote Cache-timing Attacks Against AES”, In Proceedings of the First Workshop on Cryptography and Security in Computing Systems (CS2 ’14). ACM, Vienna, Austria, pp. 45-48

[10] S. Das, J. Bhaumik, “Strengthening SPN type block cipher architecture against Fault attack”, In Proceedings of IEE Int. Conf. on Communications, Devices and Intelligent Systems (CODIS) 2012, 580-583

[11] S. Das, T. Peyret, K. Martin, P. Coussy, “Introduction d’aléas dans le processus deprojection d’applications sur CGRA,” Conférence d’informatique en Parallélisme, Architecture et Système (COMPAS 2016), Jul 2016, Lorient, France

[12] S. Das, J. Bhaumik, “Compact Implementation of AES on FPGA”, In Proceedings of National Conf. of Advanced Communication and Designing (NCACD), 2011, pp. 32-34
 

Research positions are open for graduate, senior-level undergraduate, and postgraduate students interested in doing research on architecture and compilation support for ultra-low power accelerators, co-processors for post-quantum cryptography and machine learning applications in modern multi-core heterogeneous systems. The following skill sets are desired:

• Programming with one or more of the following: C/C++/scripting languages
• Knowledge about architecture, processor, memory
• Knowledge of Hardware Description Language (HDL) (i.e. Verilog)
• Knowledge of compilation flow, high-level synthesis

Do not hesitate to contact me, e.g., by email for further details.

I recommend watching You and Your Research by Richard Hamming.