Sandeep Chandran is an Assistant Professor in the Department of Computer Science and Engineering, Indian Institute of Technology Palakkad (IITPkd). He received his PhD from Indian Institute of Technology Delhi (IITD). He has previously worked at AMD, Bangalore and Freescale Semiconductors, Noida (now NXP).
I investigate design and verification challenges when scaling high-performance systems to meet computational needs of the future. On the design front, my research focuses on using a combination of modern architectures (where there is a reconfigurable fabric alongside a processor), and system-level modifications to increase single-thread performance beyond state-of-the-art processors without compromising energy-efficiency and security. On the verification front, I focus on finding ways to make post-silicon validation techniques efficient and privacy-aware so that teams from across companies can collaborate without compromising their Intellectual Properties (IPs).
CS 5005: Parallel Programming
CS 2160: Computer Organization and Architecture Lab
Invited Book Chapter
- Debug Data Reduction Techniques by Sandeep Chandran, and Preeti Ranjan Panda, in Post-silicon Validation and Debug, SPRINGER 2018
Managing Trace Summaries to Minimize Stalls During Post-silicon Validation
Sandeep Chandran, Preeti Ranjan Panda, Smruti R. Sarangi, Ayan Bhattacharyya, Deepak Chauhan, and Sharad Kumar, IEEE TRANSACTIONS ON VLSI SYSTEMS (TVLSI), VOLUME 25, ISSUE 6, JUNE 2017
Area-aware Cache Update Trackers for Post-silicon Validation
Sandeep Chandran, Smruti R. Sarangi, and Preeti Panda, IEEE TRANSACTIONS ON VLSI SYSTEMS (TVLSI), VOLUME 24, ISSUE 5, MAY 2016
Architectural Support for Handling Jitter in Shared Memory based Parallel Applications
Sandeep Chandran, Prathmesh Kallurkar, Parul Gupta, and Smruti R. Sarangi, IEEE TRANSACTIONS ON PARALLEL AND DISTRIBUTED SYSTEMS (TPDS). VOLUME 25, ISSUE 5, MAY 2014
DHOOM: Reusing Design-for-Debug Hardware for Online Monitoring by Neetu Jindal, Sandeep Chandran, Preeti Ranjan Panda, Sanjiva Prasad, Abhay Mitra, Kunal Singhal, Shubham Gupta, and Shikhar Tuli, ACM/IEEE DESIGN AUTOMATION CONFERENCE (DAC'19), Las Vegas, USA, 2019 (accepted)
Extending Trace History Through Tapered Summaries in Post-silicon Validation
Sandeep Chandran, Preeti Ranjan Panda, Smruti R. Sarangi, Deepak Chauhan, Sharad Kumar, ACM/IEEE ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE (ASPDAC'16), Macao SAR, CHINA, 2016 (Best paper award candidate)
A Generic Implementation of Barriers using Optical Interconnects
Sandeep Chandran, Eldhose Peter, Preeti Ranjan Panda and Smruti R. Sarangi, ACM/IEEE INTERNATIONAL CONFERENCE ON VLSI DESIGN (VLSID’16), Kolkata, India, 2016.
Space Sensitive Cache Dumping for Post Silicon Validation
Sandeep Chandran, Smruti R. Sarangi, Preeti Ranjan Panda, ACM/IEEE DESIGN AUTOMATION AND TEST IN EUROPE (DATE’13), Grenoble, France, 2013.
Awards and Recognitions
IIT Delhi FITT Award for Best Industry Relevant PhD 2017-18
AMD Spotlight Award for Q3 2017
Best Paper Award Nomination at ASP-DAC 2016
Outstanding Teaching Assistant award for two consecutive semesters
TCS Research Scholar Fellowship (Scholarship for 4 years)
- TPC member and Session chair of VLSID'19
- TPC member of HiPC'19
- IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)
- IEEE Embedded Systems Letters
- International Journal of Parallel Programming (IJPP)
- Integration - the VLSI journal (Elsevier)
- Several editions of conferences such as DAC, ICCAD, DATE, ASPDAC, VLSID, ISLPED, and ESWEEK